The invention relates generally to integrated circuits and, in particular, to methods and assemblies for extending the useful lifetime of a packaged integrated circuit, such as a packaged CMOS product.
The operating requirements of integrated circuits apply stress on the devices, which may lead over time to performance and reliability problems. The useful lifetime of integrated circuits based on complementary metal oxide semiconductor (CMOS) transistors may be determined by the useful lifetime of the CMOS transistors themselves. In particular, CMOS transistors may experience shifts in electrical parameters and adverse changes in performance.
Interface degradation during operation may reduce the useful lifetime of CMOS transistors. Interface degradation may originate from an increase in trap density at device interfaces caused by voltage stress over time. Because charge carriers can become trapped in the gate dielectric of a CMOS transistor, the switching characteristics of the transistor can be permanently changed. The presence of mobile charge carriers in the gate dielectric triggers numerous physical damage processes that can drastically change the device characteristics over prolonged periods. The accumulated damage from the interaction of the mobile charge carriers with the gate dielectric can eventually cause the integrated circuit to fail as electrical parameters, such as threshold voltage, shift from their initial state due to damage accumulation.
Methods and assemblies for counteracting or reversing shifts in electrical parameters and performance degradation are needed.